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The starting NAND page location must be programmed first, followed by an ECC accumulation context
reset with an ECC enabling, if required. The NAND device accesses discussed in the following sections
must be limited to data read or write until the specified number of ECC calculations is completed.
5.2.4.12.3.1.1 ECC Result Register and ECC Computation Accumulation Size
The GPMC includes up to nine ECC result registers (GPMC_ECCj_RESULT, j = 1 to 9) to store ECC
computation results when the specified number of bytes or 16-bit words has been computed.
The ECC result registers are used sequentially; one ECC result is stored in one ECC result register on
the list, the next ECC result is stored in the next ECC result register on the list, and so forth, until the
last ECC computation. The value of the GPMC_ECCj_RESULT register value is valid only when the
programmed number of bytes or 16-bit words has been accumulated, which means that the same
number of bytes or 16-bit words has been read from or written to the NAND device in sequence.
The GPMC_ECC_CONTROL[3-0] ECCPOINTER field must be set to the correct value to select the
ECC result register to be used first in the list for the incoming ECC computation process. The
ECCPointer can be read to determine which ECC register is used in the next ECC result storage for the
ongoing ECC computation. The value of the GPMC_ECCj_RESULT register (j = 1 to 9) can be
considered valid when ECCPOINTER equals j + 1. When the GPMC_ECCj_RESULT (where j = 9) is
updated, ECCPOINTER is frozen at 10, and ECC computing is stopped (ECCENABLE = 0).
The ECC accumulator must be reset before any ECC computation accumulation process. The
GPMC_ECC_CONTROL[8] ECCCLEAR bit must be set to 1 (nonpersistent bit) to clear the accumulator
and all ECC result registers.
For each ECC result (each register, j = 1 to 9), the number of bytes or 16-bit words used for ECC
computing accumulation can be selected from between two programmable values.
The ECCjRESULTSIZE bits (j = 1 to 9) in the GPMC_ECC_SIZE_CONFIG register select which
programmable size value (ECCSIZE0 or ECCSIZE1) must be used for this ECC result (stored in
GPMC_ECCj_RESULT register ).
The ECCSIZE0 and ECCSIZE1 fields allow selection of the number of bytes or 16-bit words used for
ECC computation accumulation. Any even values from 2 to 512 are allowed.
Flexibility in the number of ECCs computed and the number of bytes or 16-bit words used in the
successive ECC computations enables different NAND page error-correction strategies. Usually based
on 256 or 512 bytes and on 128 or 256 16-bit word, the number of ECC results required is a function of
the NAND device page size. Specific ECC accumulation size can be used when computing the ECC on
the NAND spare byte.
For example, with a 2 Kbyte data page 8-bit wide NAND device, eight ECCs accumulated on 256 bytes
can be computed and added to one extra ECC computed on the 24 spare bytes area where the eight
ECC results used for comparison and correction with the computed data page ECC are stored. The
GPMC then provides nine GPMC_ECCj_RESULT registers (j= 1 to 9) to store the results. In this case,
ECCSIZE0 is set to 256, and ECCSIZE1 is set to 24; the ECC[1-8]RESULTSIZE bits are cleared to 0,
and the ECC9RESULTSIZE bit is set to 1.
5.2.4.12.3.1.2 ECC Enabling
The GPMC_ECC_CONFIG[3-1] ECCCS field selects the allocated chip-select. The
GPMC_ECC_CONFIG[0] ECCENABLE bit enables ECC computation on the next detected read or
write access to the selected chip-select.
The ECCPOINTER, ECCCLEAR, ECCSIZE, ECCjRESULTSIZE (where j = 1 to 9), ECC16B, and
ECCCS fields must not be changed or cleared while an ECC computation is in progress.
The ECC accumulator and ECC result register must not be changed or cleared while an ECC
computation is in progress.
Table 5-12
describes the ECC enable settings.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
General-Purpose Memory Controller (GPMC)
Architecture
609
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