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5.2.4.12.4.5 FIFO Control in Write-Posting Mode
The FIFO can be filled directly by the MPU or by an sDMA channel.
In MPU filling mode, the FIFO status can be monitored through the FIFOPOINTER or through the
GPMC_PREFETCH_STATUS[16] FIFOTHRESHOLDSTATUS bit. FIFOPOINTER indicates the current
number of available free byte places in the FIFO, and the FIFOTHRESHOLDSTATUS bit, when set,
indicates that at least FIFOTHRESHOLD free byte places are available in the FIFO.
An interrupt can be issued by the GPMC if the GPMC_IRQENABLE[0] FIFOEVENTENABLE bit is set.
When the interrupt is fired, the GPMC_IRQSTATUS[0] FIFOEVENTSTATUS bit is set. To clear the
interrupt, the MPU must write enough bytes to fill the FIFO, or enough bytes to get below the
programmed threshold, and the FIFOEVENTSTATUS bit must be cleared to get further interrupt events.
The FIFOEVENTSTATUS bit must always be cleared prior to asserting the FIFOEVENTENABLE bit to
clear any out-of-date logged interrupt event. This interrupt must be enabled after enabling the
STARTENGINE bit
The posting completion can be monitored through the GPMC_PREFETCH_STATUS[13-0]
COUNTVALUE field. COUNTVALUE indicates the current number of remaining data to be written
based on the TRANSFERCOUNT value. An interrupt is issued by the GPMC when the write-posting
process completes (that is, COUNTVALUE equal to 0) if the GPMC_IRQENABLE[1]
TERMINALCOUNTEVENTENABLE bit is set. When the interrupt is fired, the GPMC_IRQSTATUS[1]
TERMINALCOUNTSTATUS bit is set. To clear the interrupt, the MPU must clear the
TERMINALCOUNTSTATUS bit. The TERMINALCOUNTSTATUS bit must always be cleared prior to
asserting the TERMINALCOUNTEVENTENABLE bit to clear any out-of-date logged interrupt event.
NOTE: The COUNTVALUE value is only valid if the write-posting engine is active and started,
and an interrupt is only issued when COUNTVALUE reaches 0, that is, when the posting
engine automatically goes from active to inactive.
In DMA filling mode, the DMAMode bit field in the GPMC_PREFETCH_CONFIG1[2] DMAMODE bit
must be set so that the GPMC issues a DMA hardware request when at least FIFOTHRESHOLD
bytes-free places are available in the FIFO. The DMA channel owning this DMA request must be
programmed so that a number of bytes equal to the value programmed in the FIFOTHRESHOLD bit
field are written into the FIFO during the DMA access. The DMA request remains active until the
associated number of bytes has effectively been written into the FIFO, and no other DMA request can
be issued until the ongoing active request has been completed.
Any potentially active DMA request is cleared when the prefetch engine goes from inactive to active
prefetch (STARTENGINE set to 1). The associated DMA channel must always be enabled by the MPU
after setting the STARTENGINE bit so that an out-of-date active DMA request does not trigger spurious
DMA transfers.
In write-posting mode, the DMA or the MPU fill the FIFO with no consideration to the associated byte
enables. Any byte stored in the FIFO is written into the memory device.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
General-Purpose Memory Controller (GPMC)
Architecture
631
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