Table of Contents
Advertisement
Architecture
5.2.4.12.3.2 BCH Code (Bose-Chaudhurl-Hocquenghem)
All references to Error Code Correction (ECC) in this subsection refer to the 4- to 16-bit error correction
BCH code.
5.2.4.12.3.2.1 Requirements
Read and write accesses to a NAND flash take place by whole pages, in a predetermined sequence:
first the data byte page itself, then some spare bytes, including the BCH ECC (and other information).
The NAND IC can cache a full page, including spares, for read and write accesses.
Typical page write sequence:
•
Sequential write to NAND cache of main data + spare data, for a page. ECC is calculated on the fly.
Calculated ECC may be inserted on the fly in the spares, or replaced by dummy accesses.
•
When the calculated ECC is replaced by dummy accesses, it must be written to the cache in a
second, separate phase. The ECC module is disabled during that time.
•
NAND writes its cache line (page) to the array
Typical page read sequence:
•
Sequential read of a page. ECC is calculated on the fly.
•
ECC module buffers status determines the presence of errors.
•
Accesses to several memories may be interleaved by the GPMC, but only one of those memories
can be a NAND using the BCH engine at a time; in other words, only one BCH calculation (for
example, for a single page) can be on-going at any time. Note also that the sequential nature of
NAND accesses guarantees that the data is always written / read out in the same order.
BCH-relevant accesses are selected by the GPMCs chip-select.
•
Each page may hold up to 4 Kbytes of data, spare bytes not included. This means up to 8 x
512-byte BCH messages. Since all the data is written / read out first, followed by the BCH ECC, this
means that the BCH engine must be able to hold 8 104-bit remainders or syndromes (or smaller,
52-bit ones) at the same time.
The BCH module has the capacity to store all remainders internally. After the page start, an internal
counter is used to detect the 512-byte sector boundaries. On those boundaries, the current remainder
is stored and the divider reset for the next calculation. At the end of the page, the BCH module contains
all remainders.
•
NAND access cycles hold 8 or 16 bits of data each (1 or 2 bytes); Each NAND cycle takes at least 4
cycles of the GPMCs internal clock. This means the NAND flash timing parameters must define a
RDCYCLETIME and a WRCYCLETIME of at least 4 clock cycles after optimization when using the
BCH calculator.
•
The spare area is assumed to be large enough to hold the BCH ECC, that is, to have at least a
message of 13 bytes available per 512-byte sector of data. The zone of unused spare area by the
ECC may or may not be protected by the same ECC scheme, by extending the BCH message
beyond 512 bytes (maximum codeword is 1023-byte long, ECC included, which leaves a lot of
space to cover some spares bytes).
614
General-Purpose Memory Controller (GPMC)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Advertisement
Table of Contents
