Audio Serial Port Header Configuration; Audio Serial Port Slave/Master Mode Selection; Audio Serial Port Data Format Selection - Texas Instruments PCM4222EVM User Manual

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2.7.2
Audio Serial Port
For PCM mode, the audio data may be output via the audio serial port, which is buffered and routed to
header J6. The audio serial port header pin configuration is shown in
may be outputs or inputs, depending upon the Master or Slave mode configuration of the port
Header J6 Pin Number
1
3
5
7
2,4,6,8,9,10
In Master mode, the BCK and LRCK clocks are output pins, and are derived from the PCM4222 MCKI
clock input (pin 35). The BCK clock rate depends on the audio data format selection. The LRCK clock rate
is always equal to the output sampling rate. In Slave mode, the BCK and LRCK clocks are input pins,
sourced from an external audio serial port master, such as a digital signal processor serial port, a serial
timing generator, or a programmable logic device. Once again, the LRCK clock rate is always equal to the
desired output sampling rate. The BCK clock rate depends on the audio data format selected. Refer to the
PCM4222 datasheet
The Slave/Master mode operation is determined by the state of the S/M input (pin 39), which is controlled
via the S/M element on switch SW3.
The audio data format is selected using the FMT0 and FMT1 inputs (pins 44 and 43, respectively), which
are controlled by the FMT0 and FMT1 elements on switch SW3.
FMT0 and FMT1 switches.
Switch SW3, FMT1
LO
LO
HI
HI
SBAU124 – December 2006
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Table 7. Audio Serial Port Header Configuration
for audio serial port operational details.
Table 8
Table 8. Audio Serial Port Slave/Master Mode Selection
Switch SW3, S/M
LO
HI
Table 9. Audio Serial Port Data Format Selection
Switch SW3, FMT0
LO
HI
LO
HI
Table
Audio Serial Port Signal Name, Description
SCKO, System Clock Output (same as PCM4222 MCKI clock)
BCK, Audio Data Bit Clock Input or Output
LRCK, Audio Left/Right Word Clock Input or Output
DATA, PCM Audio Data Output
Ground
summarizes the operation of the S/M switch.
Table 9
TDM with One BCK Period Delay
Hardware Configuration
7. The BCK and LRCK clocks
Slave or Master Mode
Master
Slave
summarizes the operation for the
Audio Data Format
Left Justified
2
I
S
TDM
PCM4222EVM User's Guide
11

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