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5.2.4.12.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
Any on-going read or write access from the prefetch and write-posting engine is completed before an
access to any other chip-select can be initiated. As a default, the arbiter uses a fixed-priority algorithm,
and the prefetch and write-posting engine has the lowest priority. The maximum latency added to
access starting time in this case equals the RDCYCLETIME or WRCYCLETIME (optimized or not) plus
the requested BUSTURNAROUND delay for bus turnaround completion programmed for the chip-select
to which the NAND device is connected to.
Alternatively, a round-robin arbitration can be used to prioritize accesses to the external bus. This
arbitration scheme is enabled by setting the GPMC_PREFETCH_CONFIG1[23]
PFPWENROUNDROBIN bit. When a request to another chip-select is received while the prefetch and
write-posting engine is active, priority is given to the new request. The request processed thereafter is
the prefetch and write-posting engine request, even if another interconnect request is passed in the
mean time. The engine keeps control of the bus for an additional number of requests programmed in
the GPMC_PREFETCH_CONFIG1[19-16] PFPWWEIGHTEDPRIO bit field. Control is then passed to
the direct interconnect request.
As an example, the round-robin arbitration scheme is selected with PFPWWEIGHTEDPRIO set to 2h.
Considering the prefetch and write-posting engine and the interconnect interface are always requesting
access to the external interface, the GPMC grants priority to the direct interconnect access for one
request. The GPMC then grants priority to the engine for three requests, and finnaly back to the direct
interconnect access, until the arbiter is reset when one of the two initiators stops initiating requests.
5.3
Basic Programming Model
5.3.1 GPMC High-Level Programming Model Overview
The high-level programming model introduces a top-down approach for users that need to configure the
GPMC module.
Figure 5-42
of the diagram is described in one of the following subsections through a set of registers to configure.
Table 5-24
and
Table 5-25
SPRUGX9 – 15 April 2011
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Preliminary
shows a programming model top-level diagram for the GPMC. Each block
list each step in the model.
© 2011, Texas Instruments Incorporated
Basic Programming Model
General-Purpose Memory Controller (GPMC)
633
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