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5.2.4.10.2.1 Synchronous Single Read
Figure 5-17
and
Figure 5-18
equal to 0 and 1, respectively.
Figure 5-17. Synchronous Single Read (GPMCFCLKDIVIDER = 0)
GPMC_FCLK
CLKACTIVATIONTIME
GPMC_CLK
A[27:17]
A[16:1]/D[15:0]
nBE1/nBE0
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEONTIME
nOE
DIR
WAIT
SPRUGX9 – 15 April 2011
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Preliminary
show a synchronous single-read operation with GPMCFCLKDIVIDER
RDCYCLETIME
RDACCESSTIME
WRDATAONADMUXBUS
Valid Address
CSRDOFFTIME
OEOFFTIME
OUT
© 2011, Texas Instruments Incorporated
Valid Address
D 0
IN
General-Purpose Memory Controller (GPMC)
Architecture
OUT
587
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