Table of Contents
Advertisement
www.ti.com
After a write operation, if no other access (read or write) is pending, the data bus keeps its previous
value. See
Section
5.2.4.10.1.1.5 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
Write multiple (page) access in asynchronous mode is not supported for address/data-multiplexed
devices. If GPMC_CONFIG1_i[28] WRITEMULTIPLE is enabled (1) with GPMC_CONFIG1_i[27]
WRITETYPE as asynchronous (0), the GPMC processes single asynchronous accesses.
For accesses on non-multiplexed devices, see
5.2.4.10.1.2 Access on Address/Address/Data (AAD) Multiplexed Devices
5.2.4.10.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
Figure 5-15
shows an asynchronous single read operation on an AAD-multiplexed device.
Figure 5-15. Asynchronous Single-Read on an AAD-Multiplexed Device
GPMC_FCLK
GPMC_CLK
A[27:17]
A[16:1]/D[15:0]
nBE1/nBE0
nCS
nADV
nOE
DIR
WAIT
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Preliminary
5.2.4.9.10.
RDCYCLETIME
RDACCESSTIME
MSB Address
LSB Add
CSRDOFFTIME
CSONTIME
ADVRDOFFTIME
ADVONTIME
ADVAADMUXRDOFFTIME
ADVAADMUXONTIME
OEOFFTIME
OEONTIME
OEAADMUXOFFTIME
OEAADMUXONTIME
OUT
© 2011, Texas Instruments Incorporated
Section
5.2.4.10.3.
Valid Address
IN
General-Purpose Memory Controller (GPMC)
Architecture
Data 0
Data 0
OUT
583
Advertisement
Table of Contents
