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CSONTIME, CSRDOFFTIME and CSWROFFTIME parameters are applicable to synchronous and
asynchronous modes. CSONTIME can be used to control an address and byte enable setup time
before chip-select assertion. CSRDOFFTIME and CSWROFFTIME can be used to control an address
and byte enable hold time after chip-select deassertion.
CS signal transitions as controlled through CSONTIME, CSRDOFFTIME, and CSWROFFTIME can be
delayed by half a GPMC_FCLK period by enabling the GPMC_CONFIG2_i[7] CSEXTRADELAY bit.
This half of a GPMC_FCLK period provides more granularity on the CS assertion and deassertion time
to guarantee proper setup and hold time relative to GPMC_CLK. CSEXTRADELAY is especially useful
in configurations where GPMC_CLK and GPMC_FCLK have the same frequency, but can be used for
all GPMC configurations. If enabled, CSEXTRADELAY applies to all parameters controlling CS
transitions.
The CSEXTRADELAY bit must be used carefully to avoid control-signal overlap between successive
accesses to different chip-selects. This implies the need to program the RDCYCLETIME and
WRCYCLETIME bit fields to be greater than the CS signal-deassertion time, including the extra
half-GPMC_FCLK-period delay.
5.2.4.9.3 ADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time
(ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME /
ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIM
E)
The GPMC_CONFIG3_i[3-0] ADVONTIME field (where i = 0 to 7) defines the ADV_ALE
signal-assertion time relative to start access time. It is common to read and write accesses.
The GPMC_CONFIG3_i[12-8] ADVRDOFFTIME (read access) and GPMC_CONFIG3_i[20-16]
ADVWROFFTIME (write access) bit fields define the ADV_ALE signal-deassertion time relative to start
access time.
ADVONTIME can be used to control an address and byte enable valid setup time control before
ADV_ALE assertion. ADVRDOFFTIME and ADVWROFFTIME can be used to control an address and
byte enable valid hold time control after ADV_ALE de-assertion. ADVRDOFFTIME and
ADVWROFFTIME are applicable to both synchronous and asynchronous modes.
ADV_ALE signal transitions as controlled through ADVONTIME, ADVRDOFFTIME, and
ADVWROFFTIME can be delayed by half a GPMC_FCLK period by enabling the GPMC_CONFIG3_i[7]
ADVEXTRADELAY bit. This half of a GPMC_FCLK period provides more granularity on ADV_ALE
assertion and deassertion time to assure proper setup and hold time relative to GPMC_CLK. The
ADVEXTRADELAY configuration parameter is especially useful in configurations where GPMC_CLK
and GPMC_FCLK have the same frequency, but can be used for all GPMC configurations. If enabled,
ADVEXTRADELAY applies to all parameters controlling ADV_ALE transitions.
ADVEXTRADELAY must be used carefully to avoid control-signal overlap between successive
accesses to different chip-selects. This implies the need to program the RDCYCLETIME and
WRCYCLETIME bit fields to be greater than ADV_ALE signal-deassertion time, including the extra
half-GPMC_FCLK-period delay.
The GPMC_CONFIG3_i[6-4] ADVAADMUXONTIME, GPMC_CONFIG3_i[26-24]
ADVAADMUXRDOFFTIME, and GPMC_CONFIG3_i[30-28] ADVAADMUXWROFFTIME parameters
have the same functions as ADVONTIME, ADVRDOFFTIME, and ADVWROFFTIME, but apply to the
first address phase in the AAD-multiplexed protocol. It is the user responsibility to make sure
ADVAADMUXxxOFFTIME is programmed to a value lower than or equal to ADVxxOFFTIME.
Functionality in AAD-mux mode is undefined if the settings do not comply with this requirement.
ADVAADMUXxxOFFTIME can be programmed to the same value as ADVONTIME if no high ADV
pulse is needed between the two AAD-mux address phases, which is the typical case in synchronous
mode. In this configuration, ADV is kept low until it reaches the correct ADVxxOFFTIME.
See
Section 5.2.4.12
ADVAADMUXRDOFFTIME, ADVAADMUXWROFFTIME usage for CLE and ALE (Command / Address
Latch Enable) usage for a NAND Flash interface.
SPRUGX9 – 15 April 2011
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Preliminary
for more details on ADVONTIME, ADVRDOFFTIME, ADVWROFFTIME, and
© 2011, Texas Instruments Incorporated
General-Purpose Memory Controller (GPMC)
Architecture
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