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Virtual address decoding in 32-bit mode access mode is:
•
Bit 0,1 - are always 0, as accesses are at-least 32-bit aligned
•
Bits 2:6 - 5 bits offset into the horizontal line of the page
•
Bits 7:14 - 8 bits, that select horizontal page in the tiler container as well as the X co-ordinate of the
LUT table
•
Bits 15:19 - 5 bits offset to select the line inside the page
•
Bits 20:26 - 7 bits, that select vertical page in the tiler container and also Y co-ordinate of the LUT
table
•
Bits 27:31 - In 32 bit mode, their value is binary (01110), that is address in range
7000 0000h-77FF FFFFh
2.2.1.5
ROBIN
The re-ordering buffer and initiator node (ROBIN) is a block aimed at providing some working buffering for
converting data and responses to-and-fro between raster and tiled organizations and a master port to
connect to the SDRAM controller.
The ROBIN block does:
•
Request Forwarding
•
Buffering of Write access data and buffering of Read access Response data
•
Keeps write data ordering
•
Intra-word tiling and orientation transforms
•
Tag handling
NOTE: Both ROBIN sub-modules are not software configurable.
2.2.1.6
Section Mapping
In the device, DMM supports two unique SDRAM controllers, with a software configurable option to
interleave data between both banks, at granularity of 128 Bytes, 256 Bytes and 512 Bytes. When
accessing tiled data in 8-bit, 16-bit and 32-bit modes, which in the interleaved section of the memory, the
interleaving will happen at the tile boundary of 1KB, over-riding the interleaving definition of the section.
For optimal system performance, it is recommended to enable interleaving between the 2 EMIF banks and
thus have same sized memory on both the EMIF banks. Example : 512MB of DDR3 on EMIF bank 0 and
512MB of DDR3 on EMIF bank 1, for a total system DDR3 memory of 1GB.
NOTE: This interleaving is supported only if DDRs system connected to both the SDRAM
controllers have same electrical characteristics.
If for cost reduction, one chooses to build a system with asymmetrical memory on both EMIF banks, then
a few limited configurations can be supported by using the LISA section programming feature of DMM.
The address mapping inside the DMM is configurable through up to four sections. Each section is defined
based on:
•
Its system address: the base address of the decoding range for the section. This is the address of the
incoming access to the DMM, also referred to as System Address.
•
Its size: the encoding is the number of bits actually used in the upper 8-bits of the incoming system
address. Hence the size of the section can be a value 16MB-2GB and power of 2. With interleaving
enabled, the minimum size of the section is 32 MB.
•
Its physical address: the base address of the memory range access in the external memory controller.
It is also referred to as SDRC address.
•
The target memory controller: A section may hit either of EMIF banks or both.
•
Its interleaving definition : Interleave at 128Bytes, 256 Bytes, 512 Bytes or no interleaving.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Architecture
339
DMM/TILER
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