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Architecture
3.2
Architecture
This section discusses the architecture and basic function of the EMAC/MDIO module.
3.2.1 Clock Control
The frequencies for the transmit and receive clocks are fixed by the IEEE 802.3 specification as:
•
2.5 MHz at 10 Mbps
•
25 MHz at 100 Mbps
•
125 MHz at 1000 Mbps
All EMAC logic is clocked synchronously with the peripheral clock (SYSCLK5). The MDIO clock can be
controlled through the application software, by programming the divide-down factor in the MDIO control
register (CONTROL).
3.2.1.1
MII Clocking
In the 10/100 Mbps mode, the transmit and receive clock sources are provided from an external PHY via
the MTCLK and MRCLK pins. These clocks are inputs to the EMAC module and operate at 2.5 MHz in 10
Mbps mode and at 25 MHz in 100 Mbps mode. The MII clocking interface is not used in 1000 Mbps mode.
For timing purposes, data is transmitted and received with reference to MTCLK and MRCLK, respectively.
3.2.1.2
GMII Clocking
In the 1000 Mbps mode, the transmit and receive clock sources for 10/100 Mbps operation are provided
from an external PHY via the MTCLK and MRCLK pins, as in the MII clocking. For 1000 Mbps operation,
the receive clock is provided by an external PHY via the MRCLK pin. For transmit in 1000 Mbps mode, the
clock is sourced synchronous with the data and is provided by the EMAC to be output on the GMTCLK
pin.
The EMAC module is internally clocked at 148.5 MHz. For timing purposes, data in 10/100 Mbps mode is
transmitted and received with reference to MTCLK and MRCLK, respectively. For 1000 Mbps mode,
receive timing is the same, but transmit is relative to GMTCLK.
3.2.2 Memory Map
The EMAC peripheral includes internal memory that is used to hold information about the Ethernet
packets received and transmitted. This internal RAM is 2K × 32 bits in size. Data can be written to and
read from the EMAC internal memory by either the EMAC or the CPU. It is used to store buffer descriptors
that are 4-words (16-bytes) deep. This 8K local memory holds enough information to transfer up to 512
Ethernet packets without CPU intervention.
The packet buffer descriptors can also be placed in the internal processor memory, or in EMIF memory
(DDR). There are some tradeoffs in terms of cache performance and throughput when descriptors are
placed in the system memory, versus when they are placed in the EMAC's internal memory. Cache
performance is improved when the buffer descriptors are placed in internal memory. However, the EMAC
throughput is better when the descriptors are placed in the local EMAC RAM.
410
EMAC/MDIO Module
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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