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Introduction
2.1.4 Terminologies and Acronyms Used in this Document
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bpp—Bits per pixel
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DMM—Dynamic Memory Manager
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ELLA—Extra Low Latency Access
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GB, GiB—Both imply Giga Byte
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Initiator—A node inside the Device and is either a CPU, peripheral or DMA engine, which can be
internal bus Master. Each initiator is identified by a ConnID (Connection ID). With a limit of only 16
ConnIDs, some of the Initiators are grouped together with same ConnID.
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Interlaced—Qualifier for accesses skipping one line every line
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LISA—Local Interconnect and Synchronisation Agent
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KB, KiB—Both imply Kilo Byte.
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LUT—Look Up Table
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MMU—Memory Management Unit
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MPU—Main Processing Unit. For the Device, it is Cortex™-A8.
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PAT—Physical Address Translator
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PEG—Priority Extension Generator
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Progressive—Qualifier for line-by-line accesses
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ROBIN—Re-Ordering Buffer and Initiator Node
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Tiled access—1D or 2D Access to the tiled area, where the image data is read and written in two
dimensional format, to improve the efficiency of accesses of 2D accesses, example image macro
block. TILER Tiling and Isometric Lightweight Engine for Rotation 1D access A simple linear read or
write access request. The DMM responds with read/write from/to the contiguous memory starting with
address specified in the request.
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2D access—HD_VPSS, can generate a special access to 2D image buffers, with read/ write request,
with Height and Width information. The DMM-TILER decodes the access type based on the Height,
width and address, and responds with read/write from/to data in the physical memory, which has been
co-located, with sub-tile granularity.
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DMM/TILER
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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