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2.2.2.3
TILER Container - Summary
TILER is a 128-MB virtual container arranged in 2 dimensions as 256 × 128 pages, each of 4KB.
Each 4-KB page is has 4 tiles.
Each 1-KB tile has 64 subtiles, each of size 128 bits.
Based on the mode of access, 8/16/32 bit, the data stored can be aligned differently, as explained in the
previous section.
2.2.2.3.1 Where Will the Tiled Date Be Stored in Physical Memory?
Using PAT Direct Access Translation:
By bypassing the LUT, the entire 128MB space has to be contiguous in the physical memory. Then
each of the 8-bit 128 MB virtual container, 16-bit 128 MB virtual container, 32-bit 128 MB virtual
container and paged container, can be mapped to either the same physical 128 MB space or at
different locations. Refer to the PAT_VIEW_MAP register, which defines the base address of this 128
MB space. As can be seen, this base address is 256 MB aligned.
Using PAT In-Direct Access Translation:
A more common use case would be to use the two LUTs in the DMM to map the virtual data to
physical address, at 4KB granularity. Then the physical 128MB need not be contiguous. With two LUTs
in the system, only 256 MB of data is possible. Hence, the 8, 16, 32 bit and paged containers may
need to be aliased to same pages. For example - use one LUT to map 8-bit, 16-bit, and 32-bit
containers; hence, they would all correspond to the same physical memory pages. The other LUT
would be used to map the 128 MB contained for paged accesses, as shown in
SPRUGX9 – 15 April 2011
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Preliminary
Figure 2-21. 32-bit Sub-tile
© 2011, Texas Instruments Incorporated
Architecture
Figure
2-24.
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DMM/TILER
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