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Architecture
LISA block manages all the incoming requests to ELLA, TILER and PAT and translates then to requests to
Registers and ROBIN ports. Highest priority is given to accesses coming to the low-latency port (ELLA).
When both DMM-ROBIN ports are in use, LISA module interleaves the two ports at a programmable
boundary from 128 Bytes or more, as programmed in the DMM_LISA_MAPn registers. See sub-section on
Section Mapping for details about LISA sections programming.
2.2.1.3.1 LISA LOCK
The DMM_LISA_LOCK register is used to lock the configuration once set. If written to one, the LOCK bit
prevents further writes to all DMM_LISA_MAP_i registers. The LOCK itself cannot be written back to 0. A
reset is required to re-program the sections.
It is expected that LISA MAP is set up once during system configuration and not changed subsequently.
The LOCK feature helps accomplish this and is expected to be set once the configuration is done.
2.2.1.4
PAT, Physical Address Translator Engine
The physical address translation engine (PAT) of the DMM is composed of two 32-k entry physical
address translation vector table and a set of four refill engines. The refill engine is a specialized DMA
aimed at refilling the content of the physical address translation table.
The address translation mechanism is only available when the incoming request is hitting a page mode or
tiled mode container, i.e. when the incoming address is targeting the TILER or its aliased view in the
system addressing space. Otherwise the physical address translation logic is bypassed so that the
resulting physical address corresponds to the input address.
The PAT is supporting multiple address translation schemes, called views, which can be bound to one or
more initiator through a view mapping mechanism.
The usage of the Refill Engines is described in detail in the later section.
2.2.1.4.1 PAT Views
A PAT view defines the kind of physical address translation to perform for each tiled mode accesses
(page, 8-bit, 16-bit and 32-bit). Each mode of each PAT view can be configured to either use PAT Direct
Access Translation or PAT In-Direct Access Translation.
The PAT supports up to four unique Views, using the DMM_PAT_VIEW_MAP[0..3] Registers.
2.2.1.4.2 PAT View Mappings
The 16 groups of initiators of the Device, each identified by their ConnID, share a set of 4 PAT views. The
connection from an initiator to a PAT view is made through the DMM_PAT_VIEW register. The register
DMM_PAT_VIEW0 is used for the first eight initiator groups and DMM_PAT_VIEW1 for the second eight.
Thus each initiator can choose one of the four configurable PAT views in the system.
2.2.1.4.3 PAT View Map Base Address
The PAT view map base address is defining the base address of all PAT translated addresses. The bit 31
of all PAT translated address is set to BASE_ADDR. In the Device, the bit 31 should be set to 1, which
corresponds top 2GB assigned for external SDRAM in the system memory map. Hence the addresses
translated by PAT range in addresses 8000 0000h-FFFF FFFFh.
2.2.1.4.4 PAT - Look Up Tables (LUTs)
The PAT contains two LUTs, each of has 32K (256 × 128) entries. This geometry corresponds to that of
the Virtual TILER container. So incoming address maps the actual entry in the LUT. The PAT shall then
translate to a physical memory mapped to any 4K page the DDR. Each entry of the PAT address
corresponds to the page in the DMM container that has the same location. For example - The entry (74,
42) in the table corresponds to the page (74, 42) in any DMM container.
336
DMM/TILER
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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