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Architecture
2.2.1.8
Clock
The DMM is a synchronous design and operates from the same clock as the internal L3 interconnect. All
timings use this clock as a reference.
2.2.1.9
Interrupts
DMM module generates interrupt to Cortex™-A8, for status and error conditions related to PAT refills
engines. There 8 different conditions which can be individually enabled or disabled. With 4 Refill engines,
there are total 32 unique sources of interrupts.
Refer to
Section 2.3.3
Per Refill engine, status and error conditions are mentioned below:
1. FILL_DSCn: Refill of any descriptor, for engine n, complete.
2. FILL_LSTn: Refill of the last descriptor, for engine n, complete.
3. ERR_INV_DSCn: Invalid descriptor pointer, for engine n.
4. ERR_INV_DATAn: Invalid data table pointer, for engine n.
5. ERR_UPD_AREAn: Error caused by area register update while refilling, for engine n.
6. ERR_UPD_CTRLn: Error caused by control register update while refilling, for engine n.
7. ERR_UPD_DATAn: Error caused by data register update while refilling, for engine n.
8. ERR_LUT_MISSn: Access to a yet-to-be-filled entry, that is part of the area being refilled, for engine n.
The six error conditions mentioned above are also reported in the respective DMM_PAT_STATUSn
register.
2.2.1.10 Address Translations Within DMM, For Tiled Accesses
This section describes address translations that happen at various interfaces within DMM, for tiled
accesses.
From a user perspective, the PAT can be seen as an additional step in the process applied to the tiled
addresses by the TILER:
•
the TILER first transforms a tiled address into a 27 bit physical address which fits within a 128MB
address range.
•
the PAT then processes the high order bits of the physical address output by the TILER, and outputs a
32-bit physical address which covers a 4GB address range.
for this address translation.
The purpose of the PAT is to map the tiled data anywhere in the 4GB physical address range, with a
PAGE granularity (The TILER page is the granularity of physical memory allocation in TILER container.
Each page is 4KB). This can be summed-up in
Only the high order bits of the physical address are modified by the PAT: the 12 low-order bits remain
unchanged. This means that the data ordering within each 4kB PAGE remains as calculated by the
TILER.
A PAT view is defining the kind of physical address translation to perform for each of the page, 8-bit,
16-bit and 32-bit mode accesses. Each mode in each PAT view can be programmed in 2 different modes
(direct translation and indirect translation) which will be described in PAT section. Note that indirect mode
is the most commonly used. Direct mode is used only for debug or in case of a DMM without PAT module.
344
DMM/TILER
Preliminary
for detailed description on using the PAT refill engines.
Figure 2-11
© 2011, Texas Instruments Incorporated
Section 2.2.1.4
describes the exact details
where the PAT process appears in red.
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SPRUGX9 – 15 April 2011
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