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Section 1 Overview
1.1
SH7750 Features
The SH7750 is a 32-bit RISC (reduced instruction set computer) microprocessor, featuring object
code upward-compatibility with SH-1, SH-2, SH-3, and SH-3E microcomputers. It includes an 8-
kbyte instruction cache, a 16-kbyte operand cache with a choice of copy-back or write-through
mode, and an MMU (memory management unit) with a 64-entry fully-associative unified TLB
(translation lookaside buffer).
The SH7750 has an on-chip bus state controller (BSC) that allows direct connection to DRAM and
synchronous DRAM without external circuitry. Its 16-bit fixed-length instruction set enables
program code size to be reduced by almost 50% compared with 32-bit instructions.
The features of the SH7750 are summarized in table 1.1.
Rev. 2.0, 03/99, page 1 of 396
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