Figure 13.17 Dram Bus Cycle (Edo Mode, Rcd = 0, Anw = 0, Tpc = 1) - Hitachi SH7751 Hardware Manual

EDO Mode: With DRAM, in addition to the mode in which data is output to the data bus only
 
while the signal is asserted in a data read cycle, an EDO (extended data out) mode is also
provided in which, once the
 
signal is negated, data is output to the data bus until the
SH7751 Series, the EDO mode bit (EDOMODE) in MCR enables either normal access/burst
access using fast page mode, or EDO mode normal access/burst access, to be selected for DRAM.
When EDO mode is set, BE must be set to 1 in MCR. EDO mode normal access is shown in
figure 13.17, and burst access in figure 13.18.
CAS Negation Period: The CAS negation period can be set to 1 or 2 by means of the TCAS bit in
the MCR register.
CKIO
Address
RD/
D31–D0
(read)
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.17 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1)

 
signal is asserted while the
Tr1 Tr2 Tc1
Row


signal is asserted, even if the
 
signal is next asserted. In the
Tc2 Tce Tpc
Column
Rev. 3.0, 04/02, page 383 of 1064