Figure 13.14 Basic Dram Access Timing - Hitachi SH7751 Hardware Manual

Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in
figure 13.14. Tpc is the precharge cycle, Tr the
Tc2 the read data latch cycle.
CKIO
Address
RD/
D31–D0
(read)
D31–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Notes: IO : DACK device
SA : Single address DMA transfer
DA : Dual address DMA transfer
The DACK is in the high-active setting
For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Rev. 3.0, 04/02, page 380 of 1064


Tr1 Tr2
Row

Figure 13.14 Basic DRAM Access Timing

assert cycle, Tc1 the
Tc1 Tc2
Column
 
assert cycle, and
Tpc