Clock Stop Clear Register 00 (Clkstpclr00) - Hitachi SH7751 Hardware Manual

Bit 1—Clock Stop 1 (CSTP1): Specifies stopping of the peripheral clock supply to timer unit
(TMU) channels 3 and 4.
Bit 1: CSTP1
0
1
Bit 0—Clock Stop 0 (CSTP0): Specifies stopping of the peripheral clock supply to the interrupt
controller (INTC). When this bit is set, PCIC and TMU channel 3 and 4 interrupts are not
detected.
Bit 0: CSTP0
0
1
9.2.6

Clock Stop Clear Register 00 (CLKSTPCLR00)

Clock stop clear register 00 (CLKSTPCLR00) is a 32-bit write-only register that is used to clear
corresponding bits in the CLKSTP00 register.
Bit: 31
Initial value: 0
R/W: W
Bit: 7
Initial value: 0
R/W: W
Bits 31 to 0—Clock Stop Clear: The value of a Clock Stop Clear bit indicates whether the
corresponding Clock Stop bit is to be cleared. See section 9.2.5, Clock Stop Register 00
(CLKSTP00), for the correspondence between bits and the clocks stopped.
Bits 31 to 0
0
1
Description
Peripheral clock is supplied to TMU channels 3 and 4
Peripheral clock supply to TMU channels 3 and 4 is stopped
Description
INTC detects PCIC and TMU channel 3 and 4 interrupts
INTC does not detect PCIC and TMU channel 3 and 4 interrupts
30 29
0 0
W W
6 5
0 0
W W
Description
Corresponding Clock Stop bit is not changed
Corresponding Clock Stop bit is cleared
... 11 10
...
... 0
... W W
4 3
0 0
W W W
Rev. 3.0, 04/02, page 223 of 1064
(Initial value)
(Initial value)
9 8
0 0 0
W W
2 1 0
0 0 0
W W
(Initial value)