Table 9.1 Status Of Cpu And Peripheral Modules In Power-Down Modes - Hitachi SH7751 Hardware Manual

Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes
Power-
Down Entering
Mode Conditions CPG
Sleep SLEEP
instruction
executed
while STBY
bit is 0 in
STBCR
Deep SLEEP
sleep instruction
executed
while STBY
bit is 0 in
STBCR,
and DSLP
bit is 1 in
STBCR2
Standby SLEEP
instruction
executed
while STBY
bit is 1 in
STBCR
Hard- Setting CA
ware pin to low
standby level
Module Setting
standby MSTP bit to
1 in STBCR
Note: * The RTC operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock
(RTC)).
Rev. 3.0, 04/02, page 216 of 1064
CPU
Operating Halted
(registers
held)
Operating Halted
(registers
held)
Halted Halted
(registers
held)
Halted Halted
Operating Operating Held
Status
On-chip
On-Chip Peripheral
Memory Modules
Held Operating
Held Operating
(DMA
halted)
Held Halted*
Unde- Halted*
fined
Specified
modules
halted*
External Exiting
Pins Memory Method


Held Refresh-
ing




Held Self-
refresh-


ing


Held Self-
refresh-


ing


High- Unde-
imped- fined
ance
state


Held Refresh-
ing


Interrupt
Reset
Interrupt
Reset
Interrupt
Reset
Power-on
reset
Clearing
MSTP bit
to 0
Reset