Section 7 Instruction Set; Execution Environment - Hitachi SH7750 Programming Manual

7.1

Execution Environment

PC: At the start of instruction execution, PC indicates the address of the instruction itself.
Data sizes and data types: The SH7750's instruction set is implemented with 16-bit fixed-length
instructions. The SH7750 can use byte (8-bit), word (16-bit), longword (32-bit), and quadword
(64-bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved
to and from memory using longword or quadword size. Double-precision floating-point data (64
bits) can be moved to and from memory using longword size. When a double-precision floating-
point operation is specified (FPSCR.PR = 1), the result of an operation using quadword access will
be undefined. When the SH7750 moves byte-size or word-size data from memory to a register, the
data is sign-extended.
Load-Store Architecture: The SH7750 features a load-store architecture in which operations are
basically executed using registers. Except for bit-manipulation operations such as logical AND
that are executed directly in memory, operands in an operation that requires memory access are
loaded into registers and the operation is executed between the registers.
Delayed Branches: Except for the two branch instructions BF and BT, the SH7750's branch
instructions and RTE are delayed branches. In a delayed branch, the instruction following the
branch is executed before the branch destination instruction. This execution slot following a
delayed branch is called a delay slot. For example, the BRA execution sequence is as follows:
Static Sequence
BRA TARGET
ADD R1, R0
next_2
Delay Slot: An illegal instruction exception may occur when a specific instruction is executed in a
delay slot. See section 5, Exceptions. The instruction following BF/S or BT/S for which the
branch is not taken is also a delay slot instruction.
T Bit: The T bit in the status register (SR) is used to show the result of a compare operation, and
is referenced by a conditional branch instruction. An example of the use of a conditional branch
instruction is shown below.
ADD #1, R0 ; T bit is not changed by ADD operation
CMP/EQ R1, R0 ; If R0 = R1, T bit is set to 1
BT TARGET ; Branches to TARGET if T bit = 1 (R0 = R1)

Section 7 Instruction Set

Dynamic Sequence
BRA TARGET
ADD R1, R0
target_instr
ADD in delay slot is executed before
branching to TARGET
Rev. 2.0, 03/99, page 129 of 396