Table of Contents
Advertisement
2. IC address array write (non-associative)
The tag and V bit specified in the data field are written to the IC entry corresponding to the
entry set in the address field. The A bit in the address field should be cleared to 0.
3. IC address array write (associative)
When a write is performed with the A bit in the address field set to 1, the tag stored in the entry
specified in the address field is compared with the tag specified in the data field. If the MMU
is enabled at this time, comparison is performed after the virtual address specified by data field
bits [31:10] has been translated to a physical address using the ITLB. If the addresses match
and the V bit is 1, the V bit specified in the data field is written into the IC entry. This
operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address
translation, or the comparison shows a mismatch, no operation results and the write is not
performed. If an instruction TLB multiple hit exception occurs during address translation,
processing switches to the instruction TLB multiple hit exception handling routine.
31
Address field
1 1 1 1 0 0 0 0
31
Data field
V
: Validity bit
A
: Association bit
: Reserved bits (0 write value, undefined read value)
4.5.2
IC Data Array
The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The entry to be accessed is specified in the address field, and the longword
data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F1 indicating the IC data array, and the entry is
specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2]
are used for the longword data specification in the entry. As only longword access is used, 0
should be specified for address field bits [1:0].
The data field is used for the longword data specification.
The following two kinds of operation can be used on the IC data array:
24
23
Tag address
Figure 4.6 Memory-Mapped IC Address Array
13
12
Entry
10 9
Rev. 2.0, 03/99, page 75 of 396
5 4 3 2 1 0
A
1 0
V
Advertisement
Table of Contents
