STMicroelectronics STM32WL5 Series Reference Manual page 1435

RM0453
Table 287. CPU2 BPU register map and reset values (continued)
Offset Register name
BPU_PIDR2
0xFE8
Reset value
BPU_PIDR3
0xFEC
Reset value
BPU_CIDR0
0xFF0
Reset value
BPU_CIDR1
0xFF4
Reset value
BPU_CIDR2
0xFF8
Reset value
BPU_CIDR3
0xFFC
Reset value
Refer to
38.15 References
1. IHI 0031C (ID080813) - Arm
ADIv5.2, Issue C, 8th Aug 2013
2. DDI 0480F (ID100313) - Arm
Manual, Issue G, 16th March 2015
3. DDI 0461B (ID010111) - Arm
Reference Manual, Issue B, 10 Dec 2010
4. DDI 0314H - Arm
July, 2009
5. DDI 0403D (ID100710) - Arm
December 2014
6. DDI 0494-2a (ID062813) - Arm
Manual, Issue D, 6 July, 2015
7. DDI 0440C (ID070610) - Arm
Manual, Issue C, 29 June 2012
Section 38.13: CPU2 ROM tables
®
CoreSight™ Components Technical Reference Manual, Issue H, 10
for the register boundary addresses.
®
Debug Interface Architecture Specification ADIv5.0 to
®
CoreSight™ SoC-400 r3p2 Technical Reference
®
CoreSight™ Trace Memory Controller r0p1 Technical
®
v7-M Architecture Reference Manual, Issue E.b, 2
®
CoreSight™ ETM™-M0+ r0p1 Technical Reference
®
CoreSight™ ETM™-M4 r0p1 Technical Reference
RM0453 Rev 5
Debug support (DBG)
REVISION JEP106ID
[3:0] [6:4]
0 0 1 0 1 0 1 1
REVAND[3:0] CMOD[3:0]
0 0 0 0 0 0 0 0
PREAMBLE[7:0]
0 0 0 0 1 1 0 1
PREAMBLE
CLASS[3:0]
[11:8]
1 1 1 0 0 0 0 0
PREAMBLE[19:12]
0 0 0 0 0 1 0 1
PREAMBLE[27:20]
1 0 1 1 0 0 0 1
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