Dma Channel Primary Control Register; Dma Channel Primary Control Register Field Descriptions - Texas Instruments TMS320C6201 Reference Manual

DMA Registers
5.2.1 DMA Channel Control Registers
Figure 5–2. DMA Channel Primary Control Register
31 30 29
DST RELOAD SRC RELOAD
RW, +0 RW, +0
15 14 13
RSYNC INDEX
RW, +0 RW, +0
Table 5–3. DMA Channel Primary Control Register Field Descriptions
Field Description
DST RELOAD, Source/destination address reload for autoinitialization
SRC RELOAD
SRC/DST RELOAD = 00b: do not reload during autoinitialization
SRC/DST RELOAD = 01b: use DMA global address register B as reload
SRC/DST RELOAD = 10b: use DMA global address register C as reload
SRC/DST RELOAD = 11b: use DMA global address register D as reload
Emulation mode
EMOD
EMOD = 0: DMA channel keeps running during an emulation halt
EMOD = 1: DMA channel pauses during an emulation halt
FS Frame synchronization
FS = 0: disable
FS = 1: RSYNC event used to synchronize entire frame
TCINT Transfer controller interrupt
TCINT = 0: interrupt disabled
TCINT = 1: interrupt enabled
PRI Priority mode: DMA versus CPU
PRI = 0: CPU priority
PRI = 1: DMA priority
WSYNC, Read transfer/write transfer synchronization
RSYNC
(R/W)SYNC = 00000b: no synchronization
(R/W)SYNC = other: sets synchronization event
5-8
The DMA channel primary and secondary control registers (Figure 5–2 and
Figure 5–3) contain-fields that control each DMA channel independently. These
fields are summarized in Table 5–3 and Table 5–4.
28 27 26
EMOD FS
RW,+0 RW,+0
12 11
CNT
RELOAD
SPLIT
RW, +0 RW, +0
25 24 23
TCINT PRI
RW, +0 RW, +0
10 9 8 7 6
ESIZE DST DIR
RW, +0 RW, +0
19 18
WSYNC RSYNC
RW, +0 RW, +0
5 4 3 2 1
SRC DIR STATUS START
RW, +0 R, +0 RW, +0
Section
5.4.1.1
5.13
5.6
5.10
5.9
5.6
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