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Texas Instruments TMS320DM643 Manuals
Manuals and User Guides for Texas Instruments TMS320DM643. We have
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Texas Instruments TMS320DM643 manual available for free PDF download: User Manual
Texas Instruments TMS320DM643 User Manual (56 pages)
Texas Instruments DDR2 Memory Controller User's Guide
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 0.46 MB
Table of Contents
Table of Contents
3
Preface
6
Introduction
7
Purpose of the Peripheral
7
Features
7
Functional Block Diagram
8
Supported Use Case Statement
8
Industry Standard(S) Compliance Statement
8
Data Paths to DDR2 Memory Controller
8
Peripheral Architecture
9
Clock Control
9
DDR2 Memory Controller Clock Block Diagram
9
Memory Map
10
PLLC2 Configuration
10
Signal Descriptions
11
DDR2 Memory Controller Signals
11
DDR2 Memory Controller Signal Descriptions
11
Protocol Description(S)
12
DDR2 SDRAM Commands
12
Truth Table for DDR2 SDRAM Commands
12
Refresh Command
13
DCAB Command
14
DEAC Command
15
ACTV Command
16
DDR2 READ Command
17
DDR2 WRT Command
18
DDR2 MRS and EMRS Command
19
Memory Width and Byte Alignment
20
Byte Alignment
20
Addressable Memory Ranges
20
Endianness Considerations
21
Bit External Memory
21
Address Mapping
22
Bank Configuration Register Fields for Address Mapping
22
Logical Address-To-DDR2 SDRAM Address Map for 32-Bit SDRAM
23
Logical Address-To-DDR2 SDRAM Address Map for 16-Bit SDRAM
23
Logical Address-To-DDR2 SDRAM Address Map
24
DDR2 SDRAM Column, Row, and Bank Access
25
DDR2 Memory Controller Interface
26
DDR2 Memory Controller FIFO Block Diagram
26
DDR2 Memory Controller FIFO Description
26
Refresh Scheduling
29
2.10 Self-Refresh Mode
29
Refresh Urgency Levels
29
2.11 Reset Considerations
30
DDR2 Memory Controller Reset Block Diagram
30
Reset Sources
30
2.12 VTP IO Buffer Calibration
31
2.13 Auto-Initialization Sequence
31
DDR2 SDRAM Configuration by MRS Command
32
DDR2 SDRAM Configuration by EMRS(1) Command
32
2.14 Interrupt Support
34
2.15 DMA Event Support
34
2.16 Power Management
34
DDR2 Memory Controller Power Sleep Controller Diagram
34
2.17 Emulation Considerations
35
Supported Use Cases
36
Connecting the DDR2 Memory Controller to DDR2 Memory
36
Configuring Memory-Mapped Registers to Meet DDR2-400 Specification
36
Connecting DDR2 Memory Controller for 32-Bit Connection
37
Connecting DDR2 Memory Controller for 16-Bit Connection
37
SDRAM Bank Configuration Register (SDBCR) Configuration
38
DDR2 Memory Refresh Specification
38
SDRAM Refresh Control Register (SDRCR) Configuration
38
SDRAM Timing Register (SDTIMR) Configuration
39
SDRAM Timing Register 2 (SDTIMR2) Configuration
39
DDR2 Memory Controller Registers
40
DDR PHY Control Register (DDRPHYCR) Configuration
40
SDRAM Status Register (SDRSTAT)
41
DDR2 Memory Controller Registers Relative to Base Address 2000 0000H
41
DDR2 Memory Controller Registers Relative to Base Address 01C4 2000H
41
DDR2 Memory Controller Registers Relative to Base Address 01C4 0000H
41
SDRAM Status Register (SDRSTAT) Field Descriptions
41
SDRAM Bank Configuration Register (SDBCR)
42
SDRAM Bank Configuration Register (SDBCR) Field Descriptions
42
SDRAM Refresh Control Register (SDRCR)
44
SDRAM Refresh Control Register (SDRCR) Field Descriptions
44
SDRAM Timing Register (SDTIMR)
45
SDRAM Timing Register (SDTIMR) Field Descriptions
45
SDRAM Timing Register 2 (SDTIMR2)
46
SDRAM Timing Register 2 (SDTIMR2) Field Descriptions
46
Peripheral Bus Burst Priority Register (PBBPR)
47
Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions
47
Interrupt Raw Register (IRR)
48
Interrupt Raw Register (IRR) Field Descriptions
48
Interrupt Masked Register (IMR)
49
Interrupt Masked Register (IMR) Field Descriptions
49
Interrupt Mask Set Register (IMSR)
50
Interrupt Mask Set Register (IMSR) Field Descriptions
50
Interrupt Mask Clear Register (IMCR)
51
Interrupt Mask Clear Register (IMCR) Field Descriptions
51
DDR PHY Control Register (DDRPHYCR)
52
DDR PHY Control Register (DDRPHYCR) Field Descriptions
52
VTP IO Control Register (VTPIOCR)
53
VTP IO Control Register (VTPIOCR) Field Descriptions
53
DDR VTP Register (DDRVTPR)
54
DDR VTP Enable Register (DDRVTPER)
54
DDR VTP Register (DDRVTPR) Field Descriptions
54
DDR VTP Enable Register (DDRVTPER) Field Descriptions
54
Appendix A Revision History
55
Document Revision History
55
Important Notice
56
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