Embedded Flash Memory Interface; Introduction; Main Features; Figure 3. Flash Memory Interface Connection Inside System Architecture - ST STM32F446 Series Reference Manual

Embedded Flash memory interface

3 Embedded Flash memory interface
3.1

Introduction

The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
3.2

Main features

•
Flash memory read operations
•
Flash memory program/erase operations
•
Read / write protections
•
Prefetch on I-Code
•
64 cache lines of 128 bits on I-Code
•
8 cache lines of 128 bits on D-Code
Figure 3

Figure 3. Flash memory interface connection inside system architecture

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shows the Flash memory interface connection inside the system architecture.
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