I 2 C Bus Data Register 0 To 2 (Idar0 To Idar2) - Fujitsu F2MC-16LX Hardware Manual

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22.2.5 I C Bus Data Register 0 to 2 (IDAR0 to IDAR2)
The configuration and functions of I
described.
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I C Bus Data Register 0 to 2 (IDAR0 to IDAR2)
Figure 22.2-9 shows the bit configuration of the I
Figure 22.2-9 Bit Configuration of I
ch0:000074
ch1:00007A
ch2:000080
[bit 7 to bit 0] D7 to D0
It is a data bit.
It is the data register used for the serial transfer, and transferred from MSB. During the data receiving
(TRX= "0"), the data output value becomes "1".
The writing side of IDAR register is double buffering. If the bus is in use (BB=1), the data to be written
to is loaded to the register for serial transferring when each byte is transferred. In reading the register
for serial transferring is directly read, so the receiving data is valid only when INT bit is set.
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C bus data register 0 to 2 (IDAR0 to IDAR2) are
7 6 5
H
D7 D6 D5 D4
H
R/W R/W R/W R/W
H
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C bus data registers 0 to 2 (IDAR0 to IDAR2).
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C Bus Data Register 0 to 2 (IDAR0 to IDAR2)
4 3 2 1 0
D3 D2 D1 D0
R/W R/W R/W R/W
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CHAPTER 22 I
IDAR0 to IDAR2
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I C Bus data register
Initial value
XXXXXXXX
B
C INTERFACE
535