Mode Data; Fig. 7.2 Configuration Of Mode Data; Table 7-2 Bus Mode Setting Bits And Functions - Fujitsu MB90420/5 (A) Series Hardware Manual

7.3 Mode Data

The mode data is at memory address FFFFDF
data is input automatically to the CPU by mode fetch.
n Mode data
During of execution reset sequence, mode data at address FFFFDF
CPU core. The CPU sets the memory access mode by this mode data. The value of the mode register can
only be changed by the reset sequence. Also, the mode data setting is valid after the reset sequence.
Figure 7.2 shows the configuration of mode data.
Mode data
Bus mode setting bits
n Bus mode setting bits
The bus mode setting bits specify the operation mode after completion of the reset sequence. Table 7-2
shows the relationship between each bit and the function.
Note: In the MB90420/5 (A) series, only the single-chip mode is used, so set MD2, MD1, and MD0 to 011,
and set M1 and M0 to 00.
MODE SETTING
7
M1

Fig. 7.2 Configuration of Mode Data

Table 7-2 Bus Mode Setting Bits and Functions

M1 M0 Function
0 0 Single-chip mode
0 1
1 0 (Setting disabled)
1 1
, and specifies the operation after reset sequence. Mode
H
5 4 3
0 0 0
Remark
7-5
is input to the mode register in the
H
2 1
0 0
Function expansion bits
(reserved area)
0
0