Memory Controller (Flashcontrol, Flashreadt, Flashmwt2) - Fujitsu FR Series Application Note

Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)

3.7 Memory Controller (FLASHCONTROL, FLASHREADT, FLASHMWT2)

The memory controller must be configured, depending on the core frequency and the target
device. The startup file allows configuring the registers FCHCR, FMWT and FMWT2.
The following table shows the settings for the MB91F469G for flash read. Please check the
latest data sheet for later information.
Core clock (CLKB)
to 20 MHz
to 32 MHz
to 44 MHz
to 48 MHz
to 88 MHz
to 100 MHz
The following table shows the settings for the MB91F467D for flash read. Please check the
latest data sheet for later information.
Core clock (CLKB)
to 24 MHz
to 48 MHz
to 96 MHz
Available settings for FLASHCONTROL (FCHCR):
- B'0000000000000000
||||||||||||||||
||||||||||||||||__ SZ0
|||||||||||||||___ SZ1
||||||||||||||____ ENAB
|||||||||||||_____ LOCK
||||||||||||______ PFMC
|||||||||||_______ PFEN
||||||||||________ DBEN
|||||||||_________ FLUSH bit
||||||||__________ TAGE
|||||||___________ REN
||||||____________ Reserved
|||||_____________ Reserved
||||______________ Reserved
|||_______________ Reserved
||________________ Reserved
|_________________ Reserved
BIT[9]: REN - Non-cacheable area Range Enable
- 0 - FCHA1 defines address mask (default)
- 1 - FCHA1 defines second point for the non-cacheable address range from
FCHA0 to FCHA1
BIT[8]: TAGE - TAG RAM access Enable
- 0 - Memory mapped TAG RAM access disabled (default)
- 1 - Memory mapped TAG RAM access enabled
BIT[7]: FLUSH - Flush instruction cache entries
0 - Flushing the instruction cache entries has been completed
1 - Actually flushing the instruction cache entries
© Fujitsu Microelectronics Europe GmbH
Start91460.asm
ATD ALEH
0 0
0 0
0 0
0 0
1 1
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ATD ALEH
0 0
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- 25 -
EQ WEXH
0 -
1 -
3 -
1 -
3 -
3 -
EQ WEXH
0 0
1 0
3 0
MCU-AN-300021-E-V10
WTC
1
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WTC
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