Dma Access Operation - Fujitsu FR60 Hardware Manual

CHAPTER 4 EXTERNAL BUS INTERFACE
4.8

DMA Access Operation

This section explains DMA access operation.
■ DMA Fly-by Transfer (I/O → Memory) (TYP[3:0] = 0000
41 )
H
Figure 4.8-1 shows setting of DMA fly-by transfer (I/O → memory).
FR30
compatible
mode
Basic
mode
Setting "1" for the W01 bit of the AWR register enables the CS → RD/WR setup delay to be set. Set
•
this bit to extend the period between assertion of chip select and the read/write strobe.
Setting "1" for the W00 bit of the AWR register enables the RD/WR → CS hold delay to be set. Set this
•
bit to extend the period between negation of the read/write strobe and negation of chip select.
The CS → RD/WR setup delay (W01 bit) and RD/WR → CS hold delay (W00 bit) can be set
•
independently.
222
Figure 4.8-1 Setting of DMA Fly-by Transfer (I/O → Memory)
When a wait has not been set on the memory side
Basic cycle
MCLK
A[23:0]
AS
CSn
WRn
D[31:16]
DACKn
EOPn
DACKn
EOPn
IORD
DREQn
B
I/O wait I/O hold
cycle wait
memory address
, AWR = 0008 , and IOWR =
H
Sense timing in
demand mode