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CHAPTER 15 8/16-BIT PPG TIMER
15.2 Registers of 8/16-bit PPG Timer
15.2.1
PPG0/PPG2 Operation Mode Control Register
(PPGC0/PPGC2)
Configuration and functions of PPG0/PPG2 operation mode control register (PPGC0/
PPGC2) are described.
■ PPG0/2 Operation Mode Control Register (PPGC0/PPGC2)
The PPG0/PPG2 operation mode control register (PPGC0/PPGC2) selects the operation mode of ch.0/ch.2,
controls the pin output, selects the count clock, and controls the trigger.
Figure 15.2-2 shows the bit configuration of PPG0/PPG2 operation mode control registers (PPGC0/
PPGC2).
Figure 15.2-2 Bit Configuration of PPG0/PPG2 Operation Mode Control Registers (PPGC0/PPGC2)
bit
ch.0 : 000046
H
ch.2 : 000048
H
R/W : Readable/Writable
- :
Undefined
X :
Undefined value
The following describes functions of each bit of PPG0/PPG2 operation mode control registers (PPGC0/
PPGC2):
[bit7] PEN0: ppg Enable (operation permission)
The operation start and operation mode of PPG0/PPG2 are selected.
PEN0
0
1
• With this bit is set to "1", the PPG starts counting.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[bit6] Undefined bit
The read value is undefined. Nothing is affected when it is written.
[bit5] PE00: ppg output Enable 00 (PPG0/PPG2 output pin enabled)
Inhibition and permission of pulse output to the external pulse output pin PPG0/PPG2 are controlled.
PE00
0
1
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
344
7
6
5
4
PEN0
PE00
PIE0 PUF0
(R/W)
(R/W) (R/W) (R/W)
(0)
(X)
(0)
(0)
General-purpose port pin (pulse output interdiction).
FUJITSU MICROELECTRONICS LIMITED
3
2
1
0
Reserved
(R/W)
(0)
(X)
(X)
(1)
Operating State
Operation stop ("L" level output maintenance)
PPG Enabling Operations
Operating State
PPG0/PPG2 pulse output (pulse output permission).
MB90335 Series
PPGC0/PPGC2
PPG Operation mode control register
Read/Write
Initial value
CM44-10137-6E
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