Ppg0/Ppg2/Ppg4 Operation Mode Control Register (Ppgc0/Ppgc2/Ppgc4) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 17 8/16-BIT PPG TIMER
17.2.1 PPG0/PPG2/PPG4 Operation Mode Control Register
(PPGC0/PPGC2/PPGC4)
Configuration and functions of PPG0/PPG2/PPG4 operation mode control register
(PPGC0/PPGC2/PPGC4) are described.
PPG0/2/4 Operation Mode Control Register (PPGC0/PPGC2/PPGC4)
The PPG0/PPG2/PPG4 operation mode control register (PPGC0/PPGC2/PPGC4) selects the operation
mode of ch0/ch2/ch4, controls the pin output, selects the count clock, and controls the trigger.
Figure 17.2-2 shows the bit configuration of PPG0/PPG2/v4 operation mode control registers (PPGC0/
PPGC2/PPGC4).
Figure 17.2-2 Bit Configuration of PPG0/PPG2/PPG4 Operation Mode Control Registers
ch0 : 000046
H
ch2 : 000048
H
ch4 : 00004A
H
The following describes functions of each bit of PPG0/PPG2/PPG/4 operation mode control registers
(PPGC0/PPGC2/PPGC4):
[bit 7] PEN0: ppg Enable (operation permission)
The operation start and operation mode of PPG0/PPG2/PPG4 are selected.
PEN0
0
1
• With this bit is set to "1", the PPG starts counting.
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
[bit 6] Undefinition bit
The read value is irregular. Nothing is affected when it is written.
[bit 5] PE00: ppg output Enable 00 (PPG0/PPG2/PPG4 output pin enabled)
Inhibition and permission of pulse output to the external pulse output pin PPG0/2/4 are controlled.
PE00
0
1
• This bit is initialized to "0" at reset.
• Reading and writing are allowed.
408
(PPGC0/PPGC2/PPGC4)
7 6 5 4
−
PEN0 PE00 PIE0 PUF0
( − )
(R/W) (R/W) (R/W) (R/W)
(0) (X) (0) (0)
Operation stop ("L" level output maintenance)
PPG Enabling Operations
General-purpose port pin (pulse output interdiction).
PPG0/PPG2/PPG4 pulse output (pulse output permission).
3 2 1 0
− −
Reserved
( − ) ( − )
(R/W)
(0) (X) (X) (1)
Operating State
Operating State
PPGC0/PPGC2/PPGC4
PPG Operation mode control register
Read/Write
Initial value