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10.3.1
PPG0 Operation Mode Control Register (PPGC0)
The PPG0 operation mode control register (PPGC0) provides the following settings:
• Enabling or disabling operation of 8-/16-bit PPG timer
• Pin function switching (Enabling or disabling pulse output)
• Enabling or disabling underflow interrupt
• Setting underflow interrupt request flag
I PPG0 Operation Mode Control Register (PPGC0)
Figure 10.3-2 PPG0 Operation Mode Control Register (PPGC0)
7
6
5
R/W
R/W
R/W
: Read/Write
X
: Undefined
: Unused
: Reset value
0
4
3
2
1
R/W
R/W
W
bit0
Reserved
bit3
PUF0
bit4
PIE0
bit5
PE0
bit7
PEN0
Reset value
0 X 0 0 0 X X 1
B
Reserved bit
1
Be sure to set to "1".
Under flow generating flag bit
Read
0
Without under flow
With under flow
1
Under flow interrupt enable bit
0
Interrupt request disabled
Interrupt request enabled
1
PPG0 pin output enable bit
0
General purpose I/O port (pulse output disabled)
1
PPG0 output (pulse output enabled)
PPG0 operating enable bit
0
Count operating disabled (holding "L" level output)
Count operating inabled
1
CHAPTER 10 8/16-bit PPG timer
Write
Clear PUF0 bit
No effection
301
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