Pll Control - Fujitsu MB91260B Series Hardware Manual

3.11.1

PLL Control

The PLL oscillator circuit for the main clock can be controlled to enable/disable its
operation (oscillation) and to set the multiplier (multiplication factor).
The CLKR (clock source control register) is used to control the PLL oscillator circuit for
both items.
■ Enabling/disabling PLL Operation
The PLL1EN bit (bit10) in the CLKR (clock source control register) is used to enable or disable the
oscillation of the main PLL.
After a setting initialization reset (INIT) occurs, the PLL1EN bit is then initialized to "0", causing the main
PLL to stop oscillation. The main PLL output cannot be selected as the source clock signal while the main
PLL has its oscillation stopped.
When the device starts program operation, set the multiplier of the main PLL to be used as the clock
source, enable the PLL for oscillation, then switch the source clock after the PLL lock wait time has passed.
For this PLL lock wait time, it is recommended to use a timebase timer interrupt.
When the main PLL output has been selected as the source clock, the PLL cannot stop operation. An
attempt to write to the register is ignored. To stop the PLL, for example, before entering the stop mode,
select the frequency-halved main clock signal as the source clock signal before stopping the PLL.
If the OSCD1 bit (bit0) in the STCR (standby control register) has been set to stop oscillation during the
stop mode, the PLL stops it automatically when the device enters the stop mode, eliminating the need for
setting the stop of oscillation. When the device returns from the stop mode, the PLL restarts oscillation
automatically. If the PLL has been set to stop oscillation during the stop mode without stopping main
oscillation, the main oscillation does not stop automatically. (For returning from the stop mode then, be
sure to keep the PLL lock wait time.) In this case, stop PLL oscillation before entering the stop mode as
required.
■ PLL Multiplier
The multiplier (multiplication factor) of the main PLL is set by using the PLL1S2, PLL1S1, and PLL1S0
bits (bit14 to bit12) in the CLKR (clock source control register).
After a setting initialization reset (INIT) occurs, all of these bits are then initialized to "0".
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Setting of PLL multiplier
To change the PLL multiplier setting from the initial value, start program operation and set the new value
either before or at the same time as enabling the PLL for oscillation. After changing the multiplier, switch
the source clock after the lock wait time has passed. For this PLL lock wait time, it is recommended to use
a timebase timer interrupt.
Before changing the PLL multiplier setting during operation, switch the source clock to any resource other
than the PLL. After changing the multiplier, switch the source clock after the lock wait time has passed in
the same way as above.
The PLL multiplier setting can be changed while the PLL is being used. In this case, however, the device
enters the oscillation stabilization wait state automatically after updating the PLL multiplier and stops
program operation until the oscillation stabilization wait time has passed. When the clock source is
switched to any resource other than the PLL, the device does not stop program operation.
CHAPTER 3 CPU AND CONTROL UNITS
71