Pll Control Register (Pctr) - Fujitsu MB91150 Series Hardware Manual

3.11.7 PLL Control Register (PCTR)

The PLL control register controls PLL oscillations.
The setting of this register can be changed only when GCR CHC is 1.
I PLL control register (PCTR)
The PLL control register (PCTR) has the following configuration:
15
PCTR SLCT1
000488 (R/W)
[Bits 15 and 14]: SLCT1 and SLCT0
These bits control the Multiply ratio of the PLL. They are initialized only at power-on.
The setting of these bits indicates the internal operating frequency when GCR CHC is set to
0.
SLCT1
0
0
1
[Bits 13, 12, and 10-8]: Reserved
Always set these bits to 0. Their values during read access are undefined.
[Bit 11]: VSTP
This bit controls the PLL oscillation. It is initialized at power-on or an external reset.
If PLL is used in stopped state, it must be stopped every time the reset is canceled.
VSTP
0
1
Note:
When the stop mode is entered, the PLL stops regardless of the setting of this bit.
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
14 13 12
SLCT0 - -
(R/W)
( - ) ( - )
SLCT0 Internal operating frequency (oscillation: 16.5 MHz)
0 8.25-MHz operation [Initial value]
1 16.5-MHz operation
X 33.0-MHz operation
PLL operation
Oscillation [Initial value]
Stop of oscillation
11 10 9
VSTP - -
(R/W )
( - ) ( - )
8
Initial value
- 00XX0XXX
( - )
77