Machine Check/Interrupts; Dec 4000 Axp Fault Detection And Correction - DEC 4000 AXP Service Manual

Table 4–1 DEC 4000 AXP Fault Detection and Correction
Component
KN430 Processor Module
DECchip 21064 micropro-
cessor
Backup cache (B-cache)
MS430 Memory Modules
Memory module
KFA40 I/O Module
I/O module
System Bus
System bus

4.1.1 Machine Check/Interrupts

The exceptions that result from hardware system errors are called machine
check/interrupts. They occur when a system error is detected during the
processing of a data request. There are three types of machine check/interrupts
related to system events:
1. Processor machine check
2. System machine check
3. Processor corrected machine check
4–2 Error Log Analysis
Fault Detection/Correction Capability
Error Detection and Correction (EDC) logic. For all data
entering the 21064 microprocessor, single bits are checked
and corrected; for all data exiting the 21064 microprocessor,
the appropriate check bits are generated. A single-bit error
on any of the four longwords being read can be corrected
(per cycle).
EDC check bits on the data store; and parity on the tag
store and control store.
EDC logic protects data by detecting and correcting up to
2 bits per DRAM chip per gate array. The four bits of data
per DRAM are spread across two gate arrays (one for even
longwords, the other for odd longwords).
DSSI/SCSI buses: Data parity is checked and generated.
Lbus data transfers to Ethernet and SCSI/DSSI controllers:
Data parity is checked and generated.
Futurebus+ data transfers: Parity is checked and passed
on.
Longword parity on command, address, and data.