Figure 14.39 Write To Synchronous Dram Non-Precharge Bank (Row Miss); Figure 14.40 Write To Synchronous Dram (Row Hit) - Hitachi SH7751 Hardware Manual

CKIO
DBREQ
BAVL
TR
A25–A0
D31–D0
RAS, CAS,
WE

Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss)

CKIO
DBREQ
BAVL
TR
A25–A0
D31–D0
RAS, CAS,
WE

Figure 14.40 Write to Synchronous DRAM (Row Hit)

Rev. 3.0, 04/02, page 536 of 1064
Transfer requests can be accepted
RA
BA
PCH
CA
D0 D1 D2 D3
WT
CA
D0 D1 D2 D3
WT