Figure 22.13 Target Memory Read Cycle In Host Mode (Burst) - Hitachi SH7751 Hardware Manual

PCICLK
AD31–AD0
PAR
C/ –C/
IDSEL
Addr: PCI space address
Dn: nth data
AP: Address parity
DPn: nth data parity
Com: Command
BEn: nth data byte enable

Figure 22.13 Target Memory Read Cycle in Host Mode (Burst)

Rev. 3.0, 04/02, page 906 of 1064
Addr
AP
Com BE0
LOCKed
D0 D1 Dn
DP0 DPn-1
BE1 BEn
DPn
Disconnect