Figure 22.10 Master Memory Read Cycle In Non-Host Mode (Burst) - Hitachi SH7751 Hardware Manual

PCICLK
AD31–AD0
PAR
C/ –C/
IDSEL
/
/
Addr: PCI space address
Dn:
AP:
DPn: nth data parity
Com: Command
BEn: nth data byte enable

Figure 22.10 Master Memory Read Cycle in Non-Host Mode (Burst)

Rev. 3.0, 04/02, page 902 of 1064
Addr
Com
nth data
Address parity
D0 D1
AP DP0
BE0 BE1
Dn
DP DPn
n-1
BEn