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If data has been written to both buffers of the channel 1 FIFO, the channel 1 FIFO is busy while
data is output from one of those buffers to the PCI bus. While it is busy, data is written from the
local bus to the channel 2 FIFO, which has the next highest order of priority. When all data has
been output from the channel 1 FIFO to the PCI bus, data is output from the channel 2 FIFO,
which still contains data, to the PCI bus.
Thus, in fixed priority mode, execution alternates between the two data transfers with the highest
priority.
That is, if DMA transfers are performed simultaneously on 4 channels, the data transfers start with
alternation between channels 1 and 2 and then move to alternating between 2 and 3 when all the
data in channel 1 has been transferred. Likewise, execution moves to alternation between channels
3 and 4 on completion of channel 2.
This pattern is the same when data is transferred from the PCI bus to the local bus.
Pseudo round-robin mode (DMABT = 1): In pseudo round-robin mode, as each time data is
transferred, the order of priority is changed so that the priority level of the completed data transfer
becomes the lowest.
Regarding pseudo round-robin mode operations, refer to section 22.3.5, Host Functions.
22.3.10 Transfer Contention within PCIC
No contention occurs in the PCIC in the case of PIO transfer requests from the CPU and memory
reads/memory writes due to target transfers. This is because PIO transfers use an internal bus for
peripheral modules, and this operates independently of the local bus that has memory accessed by
external PCI devices. Contention can occur in the PCIC in the case of PIO transfer requests from
the CPU and IO reads/IO writes due to target transfers (PCIC local register access). In this case,
however, arbitration is performed in the PCIC such that priority is given to register access by the
external PCI device that has the PCI bus rights.
Rev. 3.0, 04/02, page 897 of 1064
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