Figure 22.9 Master Memory Write Cycle In Non-Host Mode (Burst) - Hitachi SH7751 Hardware Manual

PCICLK
AD31–AD0
PAR
C/ –C/
IDSEL
/
/
Addr: PCI space address
Dn:
AP:
DPn: nth data parity
Com: Command
BEn: nth data byte enable

Figure 22.9 Master Memory Write Cycle in Non-Host Mode (Burst)

Addr
Com
nth data
Address parity
D0 D1
AP DP0 DP
BE0 BE1
Rev. 3.0, 04/02, page 901 of 1064
Dn
APn
n-1
BEn