17.1.2
Block Diagram
Figure 17.1 shows a block diagram of the smart card interface.
SCRDR1
RxD
SCRSR1
TxD
SCK
SCSCMR1: Smart card mode register
SCRSR1:
Receive shift register
SCRDR1:
Receive data register
SCTSR1:
Transmit shift register
SCTDR1:
Transmit data register
SCSMR1:
Serial mode register
SCSCR1:
Serial control register
SCSSR1:
Serial status register
SCBRR1:
Bit rate register
SCSPTR1: Serial port register
Rev. 3.0, 04/02, page 680 of 1064
Module data bus
SCTDR1
SCTSR1
Parity generation
Parity check
Figure 17.1 Block Diagram of Smart Card Interface
SCSCMR1
SCBRR1
SCSSR1
SCSCR1
Baud rate
SCSMR1
generator
SCSPTR1
Transmission/
reception
control
Clock
External clock
SCI
Internal
data bus
Pφ
Pφ/4
Pφ/16
Pφ/64
TXI
RXI
ERI