Table of Contents
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Section 1
1.1
SH7751 Series Features.....................................................................................................
1.2
Block Diagram .................................................................................................................. 10
1.3
Pin Arrangement ............................................................................................................... 11
1.4
Pin Functions..................................................................................................................... 13
1.4.1
Pin Functions (256-Pin QFP) ............................................................................... 13
1.4.2
Pin Functions (256-Pin BGA) .............................................................................. 24
Section 2
2.1
Data Formats ..................................................................................................................... 35
2.2
Register Configuration ...................................................................................................... 36
2.2.1
Privileged Mode and Banks ................................................................................. 36
2.2.2
General Registers ................................................................................................. 39
2.2.3
Floating-Point Registers ....................................................................................... 41
2.2.4
Control Registers.................................................................................................. 43
2.2.5
System Registers .................................................................................................. 44
2.3
Memory-Mapped Registers ............................................................................................... 46
2.4
Data Format in Registers ................................................................................................... 47
2.5
Data Formats in Memory .................................................................................................. 47
2.6
Processor States................................................................................................................. 48
2.7
Processor Modes................................................................................................................ 49
Section 3
3.1
Overview ........................................................................................................................... 51
3.1.1
Features ................................................................................................................ 51
3.1.2
Role of the MMU ................................................................................................. 51
3.1.3
Register Configuration ......................................................................................... 54
3.1.4
Caution ................................................................................................................. 54
3.2
Register Descriptions......................................................................................................... 55
3.3
Address Space ................................................................................................................... 58
3.3.1
Physical Address Space........................................................................................ 58
3.3.2
External Memory Space ....................................................................................... 61
3.3.3
Virtual Address Space .......................................................................................... 62
3.3.4
On-Chip RAM Space ........................................................................................... 63
3.3.5
Address Translation.............................................................................................. 63
3.3.6
Single Virtual Memory Mode and Multiple Virtual Memory Mode.................... 64
3.3.7
Address Space Identifier (ASID).......................................................................... 64
3.4
TLB Functions................................................................................................................... 65
3.4.1
Unified TLB (UTLB) Configuration.................................................................... 65
Contents
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......................................................... 51
Rev. 3.0, 04/02, page v of xxxviii
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