Interrupt-Request Codes; Table 14.18 Dtr Format For Clearing Request Queues - Hitachi SH7751 Hardware Manual

Table 14.18 DTR Format for Clearing Request Queues

DMAOR.DBL DTR.ID
0 00
1 00
Note: (SH7751R) DTR.SZ = DTR[31:29], DTR.ID = DTR[27:26], DTR.MD = DTR[25:24],
DTR.COUNT[7:4] = DTR[23:20]
14.8.5

Interrupt-Request Codes

When the number of transfers specified in DMATCR has been finished and the interrupt request is
enabled (CHCR.IE = 1), a transfer-end interrupt request can be sent to the CPU from each
channel. Table 14.19 lists the interrupt-request codes that are associated with these transfer-end
interrupts.
Rev. 3.0, 04/02, page 564 of 1064
DTR.MD DTR.SZ DTR.COUNT[7:4]
10 110 *
11
10 110
*
11 0001
0010
0011
0100
0101
0110
0111
1000
Description
Clear the request queues of all channels
(1–7).
Clear the CH0 request-accepted flag
Setting prohibited
Clear the request queues of all channels
(1–7).
Clear the CH0 request-accepted flag.
Clear the CH0 request-accepted flag
Clear the CH1 request queues.
Clear the CH2 request queues.
Clear the CH3 request queues.
Clear the CH4 request queues.
Clear the CH5 request queues.
Clear the CH6 request queues.
Clear the CH7 request queues.