CKIO
A25–A0,
,
,
RD/
,
,
,
,
,
,
Normal operation
CKIO
STATUS0, STATUS1
,
,
/
,
,
,
,
,
,
A25–A0, D31–D0
DACKn, DRAKn, SCK,
TXD, TXD2, CTS2,
*
RTS2
Note: * When the PHZ bit in STBCR is set to 1, these pins go to the high-impedance state (except
for pins being used as port pins, which retain their port state).
t
t
BREQH
BREQS
t
BOFF1
Figure 23.11 Control Signal Timing
Normal
t
STD2
Figure 23.12 Pin Drive Timing for Standby Mode
t
t
BREQH
BREQS
t
t
BACKD
BACKD
Standby mode
Standby
t
BOFF2
Rev. 3.0, 04/02, page 963 of 1064
t
BON1
Normal operation
Normal
t
STD1
t
BON2