Pci Configuration Register 15 (Pciconf15) - Hitachi SH7751 Hardware Manual

22.2.13 PCI Configuration Register 15 (PCICONF15)

Bit: 31
MLAT7
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 23
MGNT7
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 15
IPIN7
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 7
ILIN7
Initial value: 0
PCI-R/W: R/W
PP Bus-R/W: R/W
The PCI configuration register 15 (PCICONF15) is a 32-bit read/partial-write register that
accommodates the maximum latency, minimum grant, interrupt pin, and interrupt line PCI
configuration registers stipulated in the PCI local bus specifications. The interrupt pins used by the
SH7751/SH7751R are read from bits 15 to 8. Bits 7 to 0 indicate to which of the interrupt request
signal lines of an interrupt controller the interrupt line is connected.
Bits 31 to 8 are fixed in hardware. Bits 7 to 0 can be written to from both the PP bus and PCI bus.
The PCICONF15 register is initialized to H'00000100 at a power-on reset and software reset.
Bits 31 to 24—Designation of Maximum Latency (MLAT7 to 0): These bits specify the
maximum time from the time the PCI master device demands bus privileges and to the time it
obtains the privileges (not supported).
Rev. 3.0, 04/02, page 832 of 1064
30 29
MLAT6 MLAT5
0 0
R R
R R
22 21
MGNT6 MGNT5
0 0
R R
R R
14 13
IPIN6 IPIN5
0 0
R R
R R
6 5
ILIN6 ILIN5
0 0
R/W R/W
R/W R/W
28 27
MLAT4 MLAT3
0 0
R R
R R
20 19
MGNT4 MGNT3 MGNT2
0 0
R R
R R
12 11
IPIN4 IPIN3
0 0
R R
R R
4 3
ILIN4 ILIN3
0 0
R/W R/W
R/W R/W
26 25
MLAT2 MLAT1 MLAT0
0 0
R R
R R
18 17
MGNT1 MGNT0
0 0
R R
R R
10 9
IPIN2 IPIN1
0 0
R R
R R
2 1
ILIN2 ILIN1
0 0
R/W R/W
R/W R/W
24
0
R
R
16
0
R
R
8
IPIN0
1
R
R
0
ILIN0
0
R/W
R/W