Figure 23.26 Synchronous Dram Auto-Precharge Write Bus Cycle: Single (Rcd [1:0] = 01, Tpc [2:0] = 001, Trwl [2:0] = 010) - Hitachi SH7751 Hardware Manual

Tr
CKIO
t
AD
Bank
Row
Precharge-sel
Row
Address
Row
t
CSD
RD/
t
RASD
DQMn
D31–D0
(write)
CKE
t
DACD
DACKn
(SA: IO → memory)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.26 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single
(RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010)
Trw Tc1 Tc2
t
AD
H/L
c1
t t
RWD RWD
t
RASD
t
t
CASD2 CASD2
t
t
DQMD
DQMD
t t
WDD WDD
c1
t
t
BSD
BSD
t
DACD
Trwl
Tc3 Tc4
t
AD
t
CSD
Rev. 3.0, 04/02, page 981 of 1064
Trwl Tpc