Exit From Module Standby Function - Hitachi SH7751 Hardware Manual

Bit
CSTP2 0
1
CSTP1 0
1
CSTP0 0
1
MSTP6 0
1
MSTP5 0
1
MSTP4 0
1
MSTP3 0
1
MSTP2 0
1
MSTP1 0
1
MSTP0 0
1
Notes: *1 The register initialized is the same as in standby mode, but initialization is not
performed if the RTC clock is not in use (see section 12, Timer Unit (TMU)).
*2 The counter operates when the START bit in RCR2 is 1 (see section 11, Realtime
Clock (RTC)).
*3 For details, see section 20.6, User Break Controller Stop Function.
*4 Terminate DMA transfers prior to making the transition to module standby mode. If you
make a transition to module standby mode while DMA transfers are in progress, the
results of those transfers cannot be guaranteed.
9.7.2

Exit from Module Standby Function

In the case of the standby control register and standby control register 2, the module standby
function is exited by writing 0 to the MSTP6–MSTP0 bits. In the case of clock stop register 00,
the module standby function is exited by writing 1 to the corresponding bit in clock stop clear
register 00.
The module standby function is not exited by means of a power-on reset via the
power-on reset caused by watchdog timer overflow.
Rev. 3.0, 04/02, page 228 of 1064
Description
Peripheral clock is supplied to PCIC
Peripheral clock supply to PCIC is stopped
Peripheral clock is supplied to TMU channels 3 and 4
Peripheral clock supply to TMU channels 3 and 4 is stopped
INTC detects PCIC and TMU channel 3 and 4 interrupts
INTC does not detect PCIC and TMU channel 3 and 4 interrupts
SQ operates
Clock supplied to SQ is stopped
UBC operates
Clock supplied to UBC is stopped*
DMAC operates
Clock supplied to DMAC is stopped*
SCIF operates
Clock supplied to SCIF is stopped
TMU operates
Clock supplied to TMU is stopped, and register is initialized*
RTC operates
Clock supplied to RTC is stopped*
SCI operates
Clock supplied to SCI is stopped
3
4
2
1


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