Break Bus Cycle Register B (Bbrb); Break Control Register (Brcr) - Hitachi SH7751 Hardware Manual

Bits 31 to 0—Break Data Mask B31 to B0 (BDMB31–BDMB0): These bits specify whether the
corresponding bit of the channel B break data (BDB31–BDB0) set in BDRB is to be masked.
Bit 31–0: BDMBn
0
1
Note: When the data bus value is included in the break conditions, the operand size should be
specified. When byte size is specified, set the same data in bits 15–8 and 7–0 of BDRB and
BDMRB.

20.2.11 Break Bus Cycle Register B (BBRB)

BBRB is the channel B bus break register. The bit configuration is the same as for BBRA.

20.2.12 Break Control Register (BRCR)

Bit: 15
CMFA
Initial value: 0
R/W: R/W
Bit: 7
DBEB
Initial value:
*
R/W: R/W
Note: *: Undefined
The break control register (BRCR) is a 16-bit readable/writable register that specifies (1) whether
channels A and B are to be used as two independent channels or in a sequential condition, (2)
whether the break is to be effected before or after instruction execution, (3) whether the BDRB
register is to be included in the channel B break conditions, and (4) whether the user break debug
function is to be used. BRCR also contains condition match flags. The CMFA, CMFB, and UBDE
bits in BRCR are initialized to 0 by a power-on reset, but retain their value in standby mode. The
value of the PCBA, DBEB, PCBB, and SEQ bits is undefined after a power-on reset or manual
reset, so these bits should be initialized by software as necessary.
Description
Channel B break data bit BDBn is included in break conditions
Channel B break data bit BDBn is masked, and not included in break
conditions
14 13
CMFB —
0 0
R/W R
6 5
PCBB —
0
*
R/W R
12 11
— — PCBA
0 0
R R R/W
4 3
— SEQ
0
*
R R/W
Rev. 3.0, 04/02, page 761 of 1064
n = 31 to 0
10 9
—
0
*
R
2 1
— — UBDE
0 0
R R R/W
8
—
0
R
0
0