Figure 13.19(4) Dram Burst Bus Cycle, Ras Down Mode Continuation (Edo Mode, Rcd = 0, Anw = 0) - Hitachi SH7751 Hardware Manual

Tnop Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce
CKIO
c1 c2 c8
Address
RD/
End of RAS down mode
D31–D0
d1 d2 d8
(read)
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.19(4) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(EDO Mode, RCD = 0, AnW = 0)
Rev. 3.0, 04/02, page 388 of 1064