Figure 13.60 Mpx Interface Timing 1 (Burst Read Cycle, Anw = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) - Hitachi SH7751 Hardware Manual

Tm1 Tmd1w Tmd1 Tmd2
CKIO
/
D31–D0
A D0 D1
RD/
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.60 MPX Interface Timing 1
(Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits)
Rev. 3.0, 04/02, page 443 of 1064